figure 1. ads-943 functional block diagram ref dac register register output register 16 bit 14 (lsb) 15 bit 13 12 t i b 12 11 bit 11 10 bit 10 9 bit 9 8 bit 8 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 (msb) timing and control logic offset adjust 23 analog input 21 start convert 18 eoc 17 +5v analog supply 22 +5v digital supply 13 digital ground 14 C5v supply 20 analog ground 19, 24 C + s/h buffer digital correction logic flash adc 1 flash adc 2 power and grounding 3 amp block diagram the low-cost ads-943 is a 14-bit, 3mhz sampling a/d converter optimized to meet the demanding dynamic-range and sampling-rate requirements of contemporary digital telecommu- nications applications. the ads-943's outstanding dynamic performance is evidenced by a peak har- monic speci? cation of C83db and a signal-to-noise ratio (snr) of 79db. additionally, the ads-943 easily achieves the 2.2mhz minimum sampling rate required by digital receivers in certain adsl, hdsl and atm applications. the ads-943 also addresses size and power constraints normally associated with these types of applications. this device requires just 5v supplies, dissipates 1.7 watts, and is packaged in a very small 24-pin ddip. although optimized for frequency-domain applications, the ads-943's dnl and noise speci- ? cations are also outstanding, thereby making it an equally impressive device for time-domain applications (graphic and medical imaging, pro- cess control, etc.). in fact, the ads-943 guarantees no missing codes to the 14-bit level over the full hi-rel operating temperature range. the functionally complete ads-943 contains a fast-settling sample-hold ampli? er, a subranging (two-pass) a/d converter, an internal reference, timing/control logic, and error-correction circuitry. digital input and output levels are ttl. the unit is edge-triggered, requiring only the rising edge of a start convert pulse to initiate a conversion. the device is offered with a bipolar input range of 2v. models are available for use in either commercial (0 to +70c) or hi-rel (C55 to +125c) operating temperature ranges. a proprietary, auto-calibrat- ing, error-correcting circuit allows the device to achieve speci? ed performance over the full hi-rel temperature range. product overview features 14-bit resolution 3mhz minimum sampling rate ideal for both frequency and time-domain applications excellent peak harmonics, C83db excellent signal-to-noise ratio, 79db no missing codes over full hi-rel temperature range 5v supplies, 1.7 watts small, 24-pin ceramic ddip or smt low cost input/output connections pin function pin function 1 bit1 (msb) 24 analog ground 2 bit 2 23 offset adjust 3 bit 3 22 +5v analog supply 4 bit 4 21 analog input 5 bit 5 20 C5v supply 6 bit 6 19 analog ground 7 bit 7 18 start convert 8 bit 8 17 eoc 9 bit 9 16 bit 14 (lsb) 10 bit 10 15 bit 13 11 bit 11 14 digital ground 12 bit 12 13 +5v digital supply ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 1 of 8
physical/environmental parameters min. typ. max. units operating temp. range, case ads-943mc, gc 0 +70 c ads-943mm, gm C55 +125 c thermal impedance jc 6 c/watt ca 24 c/watt storage temperature range C65 +150 c package type 24-pin, metal-sealed, ceramic ddip or smt weight 0.42 ounces (12 grams) absolute maximum ratings parameters limits units +12v/+15v supply (pin 22) 0 to +16 volts C12v/C15v supply (pin 24) 0 to C16 volts +5v supply (pin 13) 0 to +6 volts digital input (pin 16) C0.3 to +v dd +0.3 volts analog input (pin 20) 15 volts lead temperature (10 seconds) +300 c +25c 0 to +70c C55 to +125c analog input min. typ. max. min. typ. max. min. typ. max. units input voltage range 2 2 2 volts input resistance 280 280 280 input capacitance 6 15 6 15 6 15 pf digital input logic levels logic "1" +2.0 +2.0 +2.0 volts logic "0" +0.8 +0.8 +0.8 volts logic loading "1" +20 +20 +20 a logic loading "0" C20 C20 C20 a start convert positive pulse width ? 10 20 10 20 10 20 static performance resolution 14 14 14 bits integral nonlinearity (? n = 10khz) 0.75 0.75 1 lsb differential nonlinearity (? n = 10khz) C0.95 0.5 +1.25 C0.95 0.5 +1.25 C0.95 0.75 +1.5 lsb full scale absolute accuracy 0.15 0.4 0.15 0.4 0.4 0.6 %fsr bipolar zero error (tech note 2) 0.1 0.3 0.1 0.3 0.3 0.6 %fsr gain error (tech note 2) 0.2 0.5 0.2 0.5 0.4 1.25 % no missing codes (? n = 10khz) 14 14 14 bits no missing codes (f in = 10khz) 14 14 14 bits dynamic performance peak harmonics (C0.5db) dc to 500khz C83 C77 C83 C77 C81 C75 db 500khz to 1mhz C83 C77 C83 C77 C81 C75 db 1mhz to 1.5mhz C83 C77 C83 C77 C81 C75 db total harmonic distortion (C0.5db) dc to 500khz C80 C76 C80 C76 C78 C74 db 500khz to 1mhz C80 C76 C80 C76 C77 C73 db 1mhz to 1.5mhz C80 C76 C80 C76 C77 C73 db signal-to-noise ratio (w/o distortion, C0.5db) dc to 500khz 76 79 76 79 75 78 db 500khz to 1mhz 76 79 76 79 74 77 db 1mhz to 1.5mhz 75 78 75 78 74 77 db signal-to-noise ratio (& distortion, C0.5db) dc to 500khz 73 77 73 77 71 75 db 500khz to 1mhz 73 77 73 77 71 75 db 1mhz to 1.5mhz 73 77 73 77 71 74 db noise 125 125 125 vrms two-tone intermodulation distortion (? n = 975khz, 1.2mhz, fs = 3mhz, C0.5db) C82 C82 C82 db input bandwidth (C3db) small signal (C20db input) 30 30 30 mhz large signal (C0db input) 10 10 10 mhz feedthrough rejection (? n = 1.5mhz) 85 85 85 db slew rate 400 400 400 v/s aperture delay time +5 +5 +5 ns aperture uncertainty 2 2 2 ps rms s/h acquisition time ( to 0.003%fsr, 4v step) 208 215 208 215 208 215 ns overvoltage recovery time ? 100 333 100 333 100 333 ns a/d conversion rate 3 3 3 mhz functional specifications (t a = +25c, +v dd = +5v, 3mhz sampling rate, and a minimum 3 minute warmup ? unless otherwise speci? ed.) ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 2 of 8
technical notes footnotes: ? all power supplies must be on before applying a start convert pulse. all supplies and the clock (start convert) must be present during warmup periods. the device must be continuously converting during this time. ? contact datel for availability of other input voltage ranges. ? a 3mhz clock with a 20nsec positive pulse width is used for all production testing. when sampling at 3mhz, the start convert pulse must be between 10 and 110nsec wide or between 160 and 300nsec wide. the falling edge must not occur between 110 and 160nsec. for lower sampling rates, wider start pulses may be used. ? this is the time required before the a/d output data is valid after the analog input is back within the speci? ed range. this time is only guaranteed if the input does not exceed 2.2v (s/h saturation voltage). ? the minimum supply voltages of +4.9v and C4.9v for vdd are required for C55c operation only. the minumum limits are +4.75v and C4.75v when operating at +125c. (snr + distortion) C 1.76 + 20 log full scale amplitude actual input amplitude 6.02 ? effective bits is equal to: 1. obtaining fully speci? ed performance from the ads-943 requires care- ful attention to pc-card layout and power supply decoupling. the device's analog and digital ground systems are connected to each other internally. for optimal performance, tie all ground pins (14, 19 and 24) directly to a large analog ground plane beneath the package. bypass all power supplies to ground with 4.7f tantalum capacitors in parallel with 0.1f ceramic capacitors. locate the bypass capacitors as close to the unit as possible. 2. the ads-943 achieves its speci? ed accuracies without the need for exter- nal calibration. if required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in figures 2 and 3. when using this circuitry, or any similar offset and gain-calibration hardware, make adjustments following warmup. to avoid interaction, always adjust offset before gain. 3. applying a start convert pulse while a conversion is in progress (eoc = logic "1") will initiate a new and inaccurate conversion cycle. data for the interrupted and subsequent conversions will be invalid. 4. a passive bandpass ? lter is used at the input of the a/d for all production testing. +25c 0 to +70c C55 to +125c digital outputs min. typ. max. min. typ. max. min. typ. max. units logic levels logic "1" +2.4 +2.4 +2.4 volts logic "0" +0.4 +0.4 +0.4 volts logic loading "1" C4 C4 C4 ma logic loading "0" +4 +4 +4 ma output coding offset binary power requirements power supply ranges ? +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 C4.75 C5.0 C5.25 C4.9 C5.0 C5.25 volts power supply currents +5v supply +210 +230 +210 +230 +210 +230 ma C5v supply C180 C195 C180 C195 C180 C195 ma power dissipation 1.7 2.0 1.7 2.0 1.7 2.0 watts power supply rejection 0.05 0.05 0.05 %fsr/%v to pin21 of ads-943 C5v signal input gain adjust 1.98k 7 50 7 +5v 2k 7 figure 2. optional ads-943 gain adjust calibration circuit ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 3 of 8
0.1f 0.1f 4.7f 4.7f 22, 13 24 20 19 ads-943 C5v 20k 7 0.1f 4.7f +5v 14 C5v +5v 21 23 18 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 (lsb) eoc analog input start convert a single +5v supply should be used for both the +5v analog and +5v digital. if separate supplies are used, the difference between the two cannot exceed 100mv. ~ ~ + + + zero/ offset adjust figure 3. connection diagram calibration procedure any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. to avoid interaction, offset must be adjusted before gain. the ranges of adjustment for the circuits in figures 2 and 3 are guaranteed to compensate for the ads-943's initial accuracy errors and may not be able to compensate for additional system errors. a/d converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. this can be accomplished by connecting led's to the digital outputs and adjusting until certain led's "? icker" equally between on and off. other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. offset adjusting for the ads-943 is normally accomplished at the point where the msb is a 1 and all other output bits are 0's and the lsb just changes from a 0 to a 1. this digital output transition ideally occurs when the applied analog input is +? lsb (+122v). gain adjusting is accomplished when all bits are 1's and the lsb just changes from a 1 to a 0. this transition ideally occurs when the analog input is at +full scale minus 1? lsb's (+1.99963v). zero/offset adjust procedure 1. apply a train of pulses to the start convert input (pin 18) so the con- verter is continuously converting. 2. apply +122v to the analog input (pin 21). 3. adjust the offset potentiometer until the output bits are 10 0000 0000 0000 and the lsb ? ickers between 0 and 1. gain adjust procedure 1. apply +1.99963v to the analog input (pin 21). 2. adjust the gain potentiometer until all output bits are 1's and the lsb ? ickers between 1 and 0. 3. to con? rm proper operation of the device, vary the input signal to obtain the output coding listed in table 2. table 2. output coding for bipolar operation bipolar scale input voltage (2v range) offset binary msb lsb +fs C 1 lsb +1.99976 11 1111 1111 1111 +3/4fs +1.50000 11 1000 0000 0000 +1/2fs +1.00000 11 0000 0000 0000 0 0.00000 10 0000 0000 0000 C1/2 fs C1.00000 01 0000 0000 0000 C3/4 fs C1.50000 00 1000 0000 0000 Cfs +1 lsb 1.99976 00 0000 0000 0001 Cfs C2.00000 00 0000 0000 0000 table 1. gain and zero adjust input voltage range zero adjust +? lsb gain adjust +fs C1? lsb 2v +122v +1.99963v ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 4 of 8
output data data n valid scale is approximately 20ns per division. sampling rate = 3mhz. eoc data n-1 valid data n+1 valid invalid data 283ns typ. 35ns typ. 130ns 1. the start convert positive pulse width must be between either 10 and 110nsec or 160 and 300nsec (when sampling at 3mhz) to ensure proper operation. for sampling rates lower than 3mhz, the start pulse can be wider than 300nsec, however a minimum pulse width low of 30nsec should be maintained. a 3mhz clock with a 20nsec positive p ulse width is used for all p roduction testin g . 2. note: 10ns max. internal s/h 10ns typ. acquisition time 125ns typ. 208ns typ. 215ns max. hold conversion time 120ns min., 130ns typ., 140ns max. 50ns typ. 30ns typ. 125ns typ. start convert n n+1 333nsec 20ns typ. figure 4. ads-943 timing diagram devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. electrically-insulating, thermally-conductive "pads" may be installed underneath the package. devices should be soldered to boards rather than "socketed," and of course, minimal air ? ow over the surface can greatly help reduce the package temperature. thermal requirements all datel sampling a/d converters are fully characterized and speci- ? ed over operating temperature (case) ranges of 0 to +70c and C55 to +125c. all room-temperature (t a = +25c) production testing is performed without the use of heat sinks or forced-air cooling. thermal impedance ? gures for each device are listed in their respective speci? ca- tion tables. these devices do not normally require heat sinks; however, standard precautionary design and layout procedures should be used to ensure ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 5 of 8
figure 5. ads-943 evaluation board schematic gnd q clr ck d pr +5vf +5va +15v C15v -15v +15v C5va +5v C5v +5vf -15v -5va option +5vf q pr d ck clr +5vf +5vf +5vf +5v C5v +5va bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 ads-943 +5vd dgnd bit13 bit14 eoc trig agnd -5v ain +5va offset agnd q1 q2 q3 q4 q5 q6 q7 q8 8d 7d 6d 5d 4d 3d 2d 1d + + + + + + + C +5va +15v + + + + + c15 u6 p2 sg10 sg3 sg2 sg1 c14 c7 c13 c6 c12 c5 l7 l6 r1 c20 c4 c11 l5 l4 l3 c3 c10 c2 c9 l2 c8 c1 l1 p4 c19 sg8 sg7 u4 r2 c18 sg5 sg6 sg4 r3 c26 c27 c25 sg9 c24 c23 c16 c22 c17 c21 x1 u6 p3 jpr1 u5 p1 jpr2 u5 u1 u3 offset adjust ana. in in ana. clc402 hi2541 ana. in start convert 7 8 14 conv. start 74hct86 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 trig 74hct86 74hct573 74hct573 74hct86 hct7474 20h 20h 20k 20h 20h 20h 20h 20h hct7474 3mhz crystal 15pf 3.2k 2.2f 4 5 6 13 12 14 11 7 9 8 13 11 12 10 26 24 22 25 23 21 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 2 5 4 11 10 14 5 6 4 2 3 1 7 2 31 2 1 3 33 31 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 3 1 9 10 8 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 10 1 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 11 spare gates c1 - c7 are 20v. 2. close sg1-sg3, sg9, sg10. all resistors are in ohms. 1. unless otherwise specified all capacitors are 50v. notes: oe ce q1 q2 q3 q4 q5 q6 q7 q8 8d 7d 6d 5d 4d 3d 2d 1d u2 10 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 11 oe ce 1 ce 0.1f 0.1f 0.1f 0.1f 0.1f 2.2f 0.1f 2.2f 2.2f 0.1f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 6 +5vf (optional) (optional) (optional) (optional) 0.01f 0.01f 0.01f 0.01f 0.01f 0.01f 0.01f 0.1f u5 u5 q 3. see datel dwg a-24546 for additional information on ads-b946 evaluation board. ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 6 of 8
figure 6. ads-943 fft analysis 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 C130 C140 C150 amplitude relative to full scale (db) 0 150 300 450 600 750 900 1.05 1.20 1.35 1.5 khz khz khz khz khz khz mhz mhz mhz mh z frequency (fs = 3mhz, fin = 1.485mhz, vin = C0.5db, 16,384-point fft) figure 7. ads-943 histogram and differential nonlinearity number of occurences digital output code 0 16,384 +0.60 0.00 C0.58 0 16,384 digital output code dnl (lsb's) ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-943.b03 page 7 of 8
mechanical dimensions - inches (mm) ordering information model number operating temp. range 24-pin package accessories ads-943mc 0 to +70c ddip ads-b943 evaluation board (without ads-943) ads-943mc-c* 0 to +70c ddip hs-24 heat sinks for all ads-943 ddip models. ads-943mm C55 to +125c ddip receptacles for pc board mounting can be ordered through amp inc. part #3-331272-8 (component lead socket), 24 required. for mil-std-883 product speci? cations, contact datel. ads-943/883 C55 to +125c ddip ads-943gc 0 to +70c smt ads-943gc-c* 0 to +70c smt ads-943gm C55 to +125c smt ads-943g/883 C55 to +125c smt *rohs-6 hazardous substance compliant. product models without the "-c" suf? x are not rohs compliant. rohs-6 fabrication does n ot claim eu rohs exemption 7b C lead in solder. 0.80 max. (20.32) 0.015 (0.381) max. radius for any pin 1.31 max. (33.02) 0.100 typ. (2.540) 0.100 (2.540) 0.190 max. (4.826) 0.040 (1.016) 0.020 typ. (0.508) 0.020 (0.508) 24 13 12 1 pin 1 index 0.130 typ. (3.302) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.060 typ. (1.524) 0.010 typ. (0.254) 0.200 max. (5.080) 0.235 max. (5.969) 0.600 0.010 (15.240) 0.80 max. (20.32) 0.100 typ. (2.540) 0.100 (2.540) 0.018 0.002 (0.457) 0.100 (2.540) 0.040 (1.016) 1.31 max. (33.27) 112 13 24 1.100 (27.940) 0.190 max. (4.826) 0.010 (0.254) +0.002 C0.001 seating plane 0.025 (0.635) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating pin 1 index 24-pin ddip versions ads-943mc ads-943mm ads-943/883 24-pin surface mount versions ads-943gc ads-943gm ads-943g/883 ads-943 14-bit, 3mhz, low-distortion, sampling a/d converters . makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. www.datel.com ? e-mail: help@datel.com ?? datel 11 cabot boulevard, mans? eld, ma 02048-1151 usa itar and iso 9001/14001 registered 01 apr 2011 mda_ads-943.b03 page 8 of 8
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